CSCI E-92: Application Note 23

Addresses for off-chip RAM
--------------------------

The off-chip RAM that we are utilizing is in a separate chip on the
TWR-K70F120M board.  That chip is the MT47H64M16HR-25 with 1Gb of
16-bit wide LPDDR2 SDRAM memory.

A crossbar switch is present in the K70 to allow connections between
masters and slaves.  The DRAM controller on Slave Modules S5, S6, and
S7 is connected via the crossbar switch to all of the other K70
modules (see Figure 3-11: Crossbar switch integration on labeled page
101 (PDF page 108)).

Master Module M0 is the ARM core code bus
Master Module M1 is the ARM core system bus

The addresses used to access this off-chip RAM are defined in the K70
Sub-Family Reference Manual, Rev. 4, Oct-2015 in Chapter 4: Memory
Map.  Table 4-1: System memory map on labeled page 199 (PDF page 206)
for our Cortex-M4 core (M1) shows that,

DRAM Controller (Aliased Area) for M0 over Slave Port S5
at addresses 0x0800_0000-0x0FFF_FFFF

DRAM Controller - Write-back for M1 over Slave Port S5
at addresses 0x7000_0000-0x7FFF_FFFF

DRAM Controller - Write-through for M1 over Slave Port S5
at addresses 0x8000_0000-0x8FFF_FFFF